Plugin-Based Chip Specification Generation

Chisel and Verilog specification generation is now integrated into the main branch through the plugin interface. LLVM CIRCT builds accurate Chisel module dependency graphs.

./install.sh --with-chisel && uv run python main.py /path/to/repo --plugin chip

Cost Forecasts in the TUI Dashboard

Start FM-Agent and its terminal UI together with:

uv run python main.py /path/to/repo --dashboard

The dashboard estimates execution time, LLM calls, tokens, and cost from historical runs without calling an LLM before analysis.

插件化芯片规约生成

Chisel 和 Verilog 规约生成已通过插件接口集成到 main 分支，硬件与软件采用统一流程。LLVM CIRCT 可更准确地分析 Chisel 模块依赖关系。

./install.sh --with-chisel && uv run python main.py /path/to/repo --plugin chip

TUI 界面展示成本预测

使用 --dashboard 参数可同时启动 FM-Agent 和 TUI。TUI 会基于历史运行信息预测执行时间、LLM 调用次数、Token 和费用，正式分析前不会调用大语言模型。

uv run python main.py /path/to/repo --dashboard